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MIC58P42
CLOCK
DATA IN
A
B
D
Micrel
E
F
STROBE
C
OUTPUT
ENABLE
G
OUT N
Timing Conditions
(T A = +25 ° C, Logic Levels are V DD and V SS ), V DD = 5V
A.
B.
C.
D.
E.
F.
G.
Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ........................................................................... 75 ns
Minimum Data Active Time After Clock Pulse (Data Hold Time) .............................................................................. 75 ns
Minimum Data Pulse Width ..................................................................................................................................... 150 ns
Minimum Clock Pulse Width .................................................................................................................................... 150 ns
Minimum Time Between Clock Activation and Strobe ............................................................................................. 300 ns
Minimum Strobe Pulse Width ................................................................................................................................... 100 ns
Typical Time Between Strobe Activation and Output Transition ............................................................................. 500 ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL
DATA must appear at the input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).
The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed
(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latche s
or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OUTPUT ENABLE/
RESET pulse resets the output after a current shutdown fault. Thermal limit faults are not latched and require no reset pulse.
MIC58P42 Truth Table
Shift Register Contents
Serial
Latch Contents
Output Contents
Serial Data
Clock
Data
Strobe
Output
Input
Input
I 1
I 2
I 3 ……
I 8
Output
Input
I 1
I 2
I 3
……
I 8 Enable I 1
I 2
I 3
…… I 8
H
L
X
H
L
R1
O
R 1
R 1
R2
O
R 2 ……
R 2 ……
R 3 ……
O ……
R 7
R 7
R 8
O
R 7
R 7
R 8
L
X
X
X ……
X
X
L
R 1 R 2
R 3
……
R 8
P 1
P 2
P 3 ……
P 8
P 8
H
P 1 P 2
P 3
……
P 8
L
P 1
P 2
P 3 ……P 8
X
X
X
……
X
H
H
H
H …… H
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
7-52
October 1998
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